1. Field
The present disclosure relates to non-volatile memory and reference cell selection.
2. Background Art
Advances in semiconductor manufacturing processes, digital system architecture, and wireless infrastructure, among other things, have resulted in a vast array of electronic products, particularly consumer products, that drive demand for ever-increasing performance and density in non-volatile memory.
One means of increasing the performance and density of non-volatile memories such as flash memory, is to shrink the dimensions of the floating gate transistors that are used in flash memories. It is well-recognized that shrinking the physical dimensions of the floating gate transistor also reduces the size of the floating gate itself and thus reduces the amount of charge that can be stored. One drawback of this approach, however, is such systems are more prone to manufacturing defects.
Memory read operations are performed on a memory array cell by comparing its potential level or active conducting current against a known reference voltage or a reference current under a technology determined electric field. Reference voltage or current is typically sourced from a smaller reference array structure which can be built from memory cells or fixed voltage or current sources depending on the technology and design preferences. Each read type operation can be defined with different electric fields across the memory cell and can have its own reference source for fine tuning purposes.
Both memory cells and reference cells can suffer from similar manufacturing defects. Conventionally, the way in which a reference cell is selected for a given operation is fixed by the manufacturer. Thus, the conventional fixed reference selection scheme results in manufacturing related yield loss as well as non-ideal reference behavior during active read type operations.